Non-volatile semiconductor memory device

ABSTRACT

The present invention relates to a method of forming a non-volatile memory device such as an EEPROM device. The non-volatile memory device is formed of an array of memory cells ( 10 ) organized into rows ( 20 ) and columns ( 22 ) within a semiconductor substrate ( 100 ). Each cell ( 10 ) comprises a gate structure ( 120 ) formed of a first dielectric layer ( 122 ), a floating gate ( 124 ), a second dielectric layer ( 126 ) and a control gate ( 128 ) formed in a well ( 50 ). The memory device further comprises insulating trenches ( 200 ) formed in said substrate ( 100 ) along a direction parallel to said columns ( 22 ) and isolating each cell ( 10 ) within a column ( 22 ) from other cells ( 10 ) within adjacent columns ( 22 ).  
     FIG. 3, 3 a , 3 b

[0001] The present invention relates generally to the field ofsemiconductor devices. In particular, the present invention relates tonon-volatile semiconductor memory devices such as electrically erasableand programmable read-only memory (EEPROM) devices and flash EEPROMdevices.

[0002] An electrically erasable and programmable read-only memory(EEPROM) device typically comprises an array of M×N floating gate cellsthat may be individually addressed in order to be programmed, read orerased. As shown in FIG. 1, each cell typically comprises a source S anda drain D, e.g. n-type regions, formed in a semiconductor substrate 2,e.g. a p-type substrate. A channel CH is disposed between the source Sand the drain D. Each cell further comprises a gate structure which iscommonly formed of a floating gate FG overlying the channel CH, and acontrol gate CG overlying the floating gate FG. The floating gate FG isseparated from the surface of the semiconductor substrate 2 by a firstthin dielectric layer 4, also referred as the “tunnel oxide”, and isisolated from the control gate CG by a second dielectric layer 6.

[0003] As shown in the schematic diagram of FIG. 2, the individualmemory cells forming the array are organized into rows and columns.Individual word lines WL (WL/1 to WL/M) form control gate CG of eachcell within a row, and respective bit lines BL (BL/1 to BL/N)electrically connect the drain D of each cell within a column. Each cellwithin a column further shares source S and drain D with adjacent cells.By activating the corresponding word WL and bit BL lines, each cell maythus be individually addressed in order to be programmed or read. Thesource S of each cell within the array may be connected to a commonsource line CS as illustrated in FIG. 1. This particular feature allowsthe erasure of every memory cells within the array simultaneously, i.e.in one “flash” operation. The memory device which is illustrated in FIG.2 is therefore known as a flash EEPROM. Alternatively, the source S ofeach cell within a column may be connected to additional bit lines as inconventional EEPROM devices.

[0004] Each cell may be charged or discharged, i.e. programmed orerased, by appropriately injecting electrons into or withdrawingelectrons from the floating gate FG. Charging and discharging of thefloating gate FG occurs by tunnelling effects through the first thindielectric layer 4. Charging the floating gate FG will generally raisethe threshold voltage VT of the cell, thus also the voltage VG that mustbe applied to the control gate CG in order to create a conductive pathbetween source S and drain D. Thus, by applying a voltage to the controlgate CG which is greater than the threshold voltage of a discharged cellbut lower than the threshold voltage of a charged cell, the state of thecell can be determined by sensing the current flowing between drain Dand source S of the memory cell. Accordingly, an unprogrammed cell willconduct, representing the logic state “zero”, whereas a programmed cellwill not conduct, representing the logic state “one”.

[0005] The performance of the cell, i.e. the ability to performprogramming and erasing operation, is essentially related to thecapacitive coupling existing between control gate CG and floating gateFG. Maximizing this capacitive coupling will facilitate programming anderasing of the cell. This implies increasing the capacitance between thefloating gate FG and the control gate CG. One will thus seek to increasethe surface area between the floating gate FG and the control gate CG.However one will also wish to reduce the surface area of the memorydevice in order to increase the density of the device and reduce thecosts of manufacture. In order to achieve both of these contradictoryobjectives, there is known from the prior art to form a memory cell in atrench structure. For instance, U.S. Pat. No. 4,979,004 discloses amethod of forming an electrically programmable read-only memory (EPROM)device comprising a plurality of trenched memory cells. The capacitivecoupling between the floating gate and the control gate is increasedwhereas the surface area is kept minimal because the two gates overlapeach other vertically in the trench.

[0006] The method disclosed in this patent can be applied to formelectrically erasable and programmable read-only memory (EEPROM) devicesbut has however some drawbacks. In particular, prior to the etchingprocesses which are ultimately performed in order to form the individualcells, the first dielectric layer and the first conductive layer of eachcell within a column therefore form a continuous lining along the trenchinterior. After the formation of the second dielectric layer and thesecond conductive layer, an anisotropic etching process is thusperformed in order to form the respective gate structures and wordlines. Consequently, in order to separate each memory cell within atrench, i.e within a column, the etching process has to be performeduntil the first dielectric layer lying at the bottom of the trench isreached. Despite the use of highly anisotropic etching processes,defects will be induced in the dielectric layers eventually causingcurrent leakage problems between the control gate and the floating gateand between the floating gate and the substrate, thus impairing theperformance and data endurance of the memory device. In the case ofEEPROM devices, it is more than likely that these problems will appearas the first dielectric layer, i.e. the tunnel oxide, is very thin sothat the tunnelling effect can occur.

[0007] Thus, the present invention has as a purpose to overcome theinconveniences of the prior art and to provide a method of forming anEEPROM device which has improved performances and reduced surface area.

[0008] The present invention also has as a purpose to provide a methodof forming an EEPROM device which is more reliable than that known fromthe prior art.

[0009] To this effect, the present invention has as object a method offorming a non-volatile memory device according to claim 1.

[0010] An advantage of the present invention lies in the fact that thesurface area of the memory device is substantially reduced. Indeed, dueto the fact that each memory cell is formed in a well, the whole surfaceof the memory device is reduced.

[0011] Another advantage of the present invention lies in the fact thatthe costs of manufacture of the semiconductor device are reduced.

[0012] Another advantage of the present invention lies in the fact thatthe capacitive coupling between the floating gate and the control gateof the memory cells is improved. Indeed, the control gate overlaps thefloating gate along the sidewalls of the well, thereby increasing thecapacitance between the two gates. Accordingly, the performances of thememory device are improved.

[0013] Still another advantage of the present invention lies in the factthat the memory cells are more reliable than those of the prior artbecause they are formed in wells rather than trenches. The drawbacks ofthe prior art method are thus avoided.

[0014] Other characteristics and advantages of the present inventionwill appear in the following description given only by way of exampleand made by referring to the drawings in which:

[0015]FIG. 1 illustrates a non-volatile memory cell of the prior art;

[0016]FIG. 2 is a schematic diagram of an array of memory cells formingan EEPROM device;

[0017] FIGS. 3 to 5 and 7 are plan views illustrating different stagesin the formation of an EEPROM device according to the present invention;

[0018]FIGS. 3a to 8 a are cross-sectional views corresponding to FIGS. 3to 5 and 7 taken along line A-A;

[0019]FIGS. 3b to 8 b are cross-sectional views corresponding to FIGS. 3to 5 and 7 taken along line B-B.

[0020]FIG. 3 illustrates a partial plan view of an embodiment of anEEPROM device according to the present invention. The device is formedof an array of EEPROM cells 10 organized into rows 20 and columns 22.FIG. 3a and 3 b are cross-sectional views of the EEPROM array takenrespectively along line A-A parallel to rows 20 and line B-B parallel tocolumns 22 as shown in FIG. 3. Insulating trenches 200 are formed in asemiconductor substrate 100 along a direction parallel to columns 22.Source 152 and drain 154 formed in the semiconductor substrate 100 arealternated between the cells 10 along each column 22. The insulatingtrenches 200 are interrupted at periodic intervals so that the source152 of each cell 10 within rows 20 is connected to a common source lineCS. It should be pointed out that this feature is not limitative and isonly required to form so-called flash EEPROM devices. The insulatingtrenches 200 may nevertheless be continuous and separate each source 152along rows 20 so as to form conventional EEPROM devices in which theEEPROM cells 10 are erased individually.

[0021] As shown in FIG. 3a and 3 b, each cell 10 is formed in a well 50and comprises a first thin dielectric layer 122 of approximately 50-100Angstroms disposed at least over the surface of the well 50. A gatestructure 120 comprising a floating gate 124, a control gate 128 and asecond dielectric layer 126 isolating the floating gate 124 from thecontrol gate 128 is formed inside each well 50.

[0022] It is to be pointed out that, for sake of clarity, the firstdielectric layer 122 is not shown on the plan view of FIG. 3 so that theunderlying insulating trenches 200, as well as the source 152 and drain154 regions may clearly be seen. This applies also for the plan viewillustrated in FIG. 7.

[0023] As shown in the upper part of FIG. 3 and in FIG. 3b, the controlgates 128 of each cell 10 within a row 20 are formed integral toindividual word lines WL. In the lower part of FIG. 3, these word linesWL and the second dielectric layer 126 have not been drawn so as to showthe floating gate 124 of each cell 10.

[0024] From the drawings of FIGS. 3, 3a and 3 b, it may be seen that thefloating gate 124 and control gate 128 of each cell 10 overlap eachother along the sidewalls of the wells 50 thus increasing thecapacitance between the two gates. It may furthermore be seen that thefloating gate 124 overlaps the insulating material of the insulatingtrenches 200 along rows 20. Thus, while the capacitance between thefloating gate 124 and control gate 128 is increased because they overlapeach other along the four sidewalls of the well 50, the capacitivecoupling between the floating gate 124 and the substrate 100 is notincreased because they overlap each other only along two sidewalls ofthe well 50, i.e. along the source 152 and the drain 154.

[0025] Referring now to FIGS. 4 to 8, a method of forming the EEPROMdevice shown in the preceding figures will be described.

[0026] As shown in FIGS. 4, 4a and 4 b, a blanket implant is performedresulting in the formation of a uniformly doped region 150 in thesurface of the substrate 100, as shown in the cross-sectional views ofFIGS. 4a and 4 b taken respectively along lines A-A and B-B. Then,insulating trenches 200 which are deeper than the depth of the dopedregion 150 are formed in the semiconductor substrate 100. Theseinsulating trenches 200 are typically formed by etching trenches in thesubstrate 100 and filling them with insulating material, e.g. silicondioxide. As a result, a grid pattern, wherein insulating trenches 200and doped regions 150 are alternated, is defined in the semiconductorsubstrate 100.

[0027] By performing a blanket implant at this early stage, no maskneeds to be used to form the source and drain regions as these aresubsequently defined by the formation of the insulating trenches 200 andwells 50. Furthermore, the implant is performed before any layer isdeposited on the substrate. Accordingly, the damages induced by theimplant are kept minimal.

[0028] Next, as shown in FIGS. 5, portions of the substrate 100 areselectively etched to form wells 50 between the insulating trenches 200.Such wells 50 are commonly formed by masking and patterning the surfaceof the substrate 100 and then etching the substrate 100 so as to formwells 50 having essentially vertical sidewalls. As shown in FIG. 5a and5 b, wells 50 are formed to a depth which is greater than the depth ofthe doped region 150, so that the doped region 150 is separated intosource 152 and drain 154 regions, a bottom surface 52 of the well 50defining a channel 156 between source 152 and drain 154. Each well 50thus comprises a first pair of facing sidewalls 54 adjacent to thesource 152 and drain 154 and a second pair of facing sidewalls 56adjacent to the insulating trenches 200

[0029] After the formation of the wells 50, it is preferable to form athin layer of oxide over the surface of the wells 50, then perform ahigh temperature annealling process in order to activate the implant,and finally strip the thin layer. These additional steps willsubstantially remove the damages or defects introduced on the surface ofthe wells 50 following the etching process.

[0030] Next, as shown in FIGS. 6a and 6 b, a first dielectric layer 122,which will ultimately form the tunnel oxide of the EEPROM cells 10, issuitably grown over the surface of the substrate and over the surface ofthe wells 50 by thermal oxidation. A first conductive layer 124, fromwhich the floating gates of the EEPROM cells will ultimately be formed,is then deposited over the first dielectric layer 122. This conductivelayer suitably comprises doped polycrystalline silicon and may bedeposited by conventional CVD techniques.

[0031] Next, with reference to FIGS. 7, 7a and 7 b, portions of thefirst conductive layer 124 are then selectively removed in order todefine strips overlying the wells 50 along a direction parallel tocolumns 22. The portions of the first conductive layer 124 may besuitably removed by conventional masking and etching processes.

[0032] Then, as shown in FIG. 8a and 8 b, a second dielectric layer 126,such as an ONO (oxide-nitrite-oxide) layer, is formed overlying thefirst conductive layer 124. A second conductive layer 128, from whichthe control gates of the EEPROM cells will ultimately be formed, is thendeposited over the dielectric layer 126 by any suitable technique, e.g.CVD.

[0033] The array of EEPROM cells is finally completed by removingportions of the first and second conductive layers 124 and 128 and thesecond dielectric layer 126 in order to form the gate structures 120overlying the wells 50 along a direction parallel to rows 20. As aresult, individual floating gates overlying the wells 50 are formed, andthe control gates of each cells in rows 20 are formed integral toindividual word lines WL. It is to be pointed out, that, in contrast tothe prior art method, the etching processes which need to be performedto form the individual gate structures 120 are not critical because thefirst and second conductive layers 124 and 128 and the second dielectriclayer 126 are etched at portions where they extend horizontally over thesurface of the semiconductor substrate 100, and not inside a trench asthis is the case in the prior art method. Accordingly, the likelihoodthat current leakage problems will occur is limited.

[0034] While the invention has been described with reference to specificembodiments, it should be clearly understood that various modificationswill be apparent to and can readily be made by those skilled in the artwithout departing from the scope of the present invention. Accordingly,it is not intended that the present invention should merely berestricted to the specific embodiments described hereinabove but shouldalso include features treated as equivalents thereof by those skilled inthe art.

What is claimed is
 1. A method of forming a non-volatile semiconductormemory device, said device being formed of an array of memory cellsorganized into rows and columns within a semiconductor substrate,wherein the method comprises the steps of: a) performing a blanketimplant in the semiconductor substrate resulting in the formation of auniformly doped region; b) forming insulating trenches in saidsemiconductor substratein a direction parallel to said columns; c)forming wellsin said substrate between said insulating trenches, so asto define alternated source and drain regions along said columns, eachof said wells having a bottom surface and having first and second pairsof facing sidewalls being respectively adjacent to said source and drainregions and to said insulating trenches; d) forming a first dielectriclayer over the surface of said substrate and said wells; e) forming afirst conductive layer over said first dielectric layer; f) removingportions of said first conductive layer, so as to define stripsoverlying said wells in a direction parallel to said columns; g) forminga second dielectric layer over said first conductive layer; h) forming asecond conductive layer over said second dielectric layer; and i)removing portions of said first and second conductive layers and saidsecond dielectric layer, so as to define gate structures overlying saidwells along said rows.
 2. A method according to claim 1, wherein itfurther comprises, directly following the formation of said wellsaccording to step c), the steps of: aa) forming a thin layer of oxideover the surface of said wells; bb) performing a high temperatureannealling process; and cc) stripping said thin layer of oxide.
 3. Amethod according to claim 1 or 2, wherein said insulating trenches areinterrupted at periodic intervals so that the source regions of thememory cell form a common source line.
 4. A non-volatile memory deviceformed of an array of memory cells organized into rows and columns, eachof said cells comprising source, drain and channel formed in asemiconductor substrate and a gate structure overlying said channel andcomprising a first dielectric layer, a floating gate, a seconddielectric layer and a control gate, wherein each of said cells isformed in a well, said memory device further comprising insulatingtrenches formed in said substrate along a direction parallel to saidcolumns and isolating each cell within a column from other cells withinadjacent columns.
 5. A non-volatile memory device according to claim 4,wherein said insulating trenches are interrupted at periodic intervalsso that the source regions of the memory cells form a common sourceline.